To do a verilog project with testbench

Hello everyone, I need a project in Verilog for sending bits from PC to FPGA. And then the FPGA process the data and send it to a MCU. The output must be 1 bit/clock cycle. The idea is send the data using Matlab, so Matlab code would also be required. A clock signal and a load signal are also required. The load signal must be in high just only while the bits are being sent to the MCU and then goes to low level.