FPGA Design and Asic

Hi there , I am Electrical + Software engineer with 19 years experience . I am interested in your project,Kindly send me a private chat message since this is a public post . Project :FPGA Design and Asic

I have long experience with FPGA and VHDL . I work with both intel and Xilinx FPGAs , SoC and SOPC. I use Quartus II and Vivado IDEs accordingly. I test timing compliance through timing analysis . I deliver tested , neat and well-commented code that can be reused or modified for future development. More to be discussed once you contact me . BR, M.T.

A proposal has not yet been provided

Hello! Only after seeing the slides you created did I realise that the latency if DD3 is similar to that of GDDR5 and thus this is actually feasible! I have worked on a ethminer port to Cell/Broadband Engine (CBE) in the past, i.e. the PS3. The project didn't go very far but involved things like managing the data bus between the main processor(PPU) and the "synergetic" processors (SPU), cache management for SPU controller, and many optimisations so that the code kept running on the PPU and SPUs as fast as possible. So I believe I know the ethereum source quite well. Currently I am working on making a Neural net lib with a hobby group that utilises an FPGA. I haven't written mining code on an FPGA before though. Also I think that the ZCash algorithm is quite conducive to mining. It requires 50 mB memory and arria 10 gt 1150, a rather new FPGA, has 53 mB DRAM!!! Compare that to 2 mB L3 cache (which is DRAM) that most processors have.

A proposal has not yet been provided

I am an electromechanical engineer , i have many skills in elecrical engineering , i can succeed your project .

Hi We are experts having 10+ years of experience in creating design using VerilogHDL, verification and validation in FPGA boards. We would like to understand more about your project, request you to plan for a brief discussion. Thanks and Regards VerifChef