Fpgaεργασίες

He have a need for an experienced PCB designer in the San Francisco Bay area. Candidate will need to come to company site to at times work the engineer. Schematic design was done in Orcad 16.5, and PCB layout to be done in PADS or PCAD. Must be familiar with decoupling high speed components, controlled impedance, differential signals, EMC, FPGA layout, high frequency analog signals and ESD. Individual must be a self-starter, have mechanical chops, a good communicator and creative. We need to have one board updated immediately, and if it seems like a fit between you and us, there are several more boards we need to have done.

Need to evaluate the FPGA prototyping board Altera cyclone 2 DE1 to design a voice recorder. Design the project using design should be able to record a minimum of 1 minute of audio input and playback clearly through the on-board speaker or an external speaker. In need of the VHDL programme codes and a Report on the analysis and how the design is done.

Xilinx ISE Project – VHDL design for Virtex 6 FPGA The task is to create a Xilinx ISE project to work with the Xilinx ML605 development board and a mating DAC board. The DAC board comes from a company called 4DSP, model FMC204. See Handbook for FMC204 board attached. The ML605 from Xilinx is a development board for the Virtex 6 FPGA. See The FMC204 board plugs into the ML605 via the high density FMC connector. The project is to generate a simple sine wave at 28MHz in the FPGA and have the DAC board produce 4 analogue output signals. The clock on the DAC board is to run at 112Mhz and provide a reference clock to the FPGA. The DAC sample frequency is also 112Msps. There are

The FPGA will replace funcionality presently , implemented via 16 CMOS ICs, gates, monostables, etc. The circuit itself is a frequency multiplier.

1. SAR ( synthetic aperture imaging radar )- 2. detection algorithm 3. compression algorithm all these 3 developed in VHDL or may in matlab FFT - in FPGA ( field programming gate array ) parallel and make a architecture with VHDL and compare with different software

1. SAR ( synthetic aperture imaging radar )- 2. detection algorithm 3. compression algorithm all these 3 developed in VHDL or may in matlab FFT - in FPGA ( field programming gate array ) parallel and make a architecture with VHDL and compare with different software

I need quotes from programmers who can build websites based off of three core templates... 1) - a money exchange site. I'd need you to program it with full functionality between currencies. 2) - a Bitcoin mining site. A site where mining pools can exchange and where forums exist around the industry news...functionality between currencies. 2) - a Bitcoin mining site. A site where mining pools can exchange and where forums exist around the industry news. 3) - an escrow service for bitcoin allowing it to be exchanged through a currency exchange. In addition... If there are any hardware geeks out there... Quote me separately in your reply on whether you can build FPGA boards and if so, how much they'd cost. Thanks!

I want to protect my IP cores, targeting Xilinx FPGAs, by using a 1-Wire EEPROM with SH...want to use DS28E01-100 EEPROM instead. I compiled the sources but the design is not working with DS28E01-100 EEPROMs. Some more points: 1 - You have to change the xapp780 sources so that it it works with DS28E01-100 EEPROM. 2 - We need 2 designs as it is in xapp780, loader and tester. Loader programs the EEPROM with our security key. Tester checks if the SHA keys are matching. 3 - Target FPGA is XC3S200AN. So, please bid if you have a Spartan 3A or 3AN evaluation kit. 4 - We use the big SFN package with 2 pins. Therefore it is very easy to connect the evaluation kit with the EEPROM through 2 cables. We will also provide some EEPROMs for testing. 5 - You will deliver me the complete so...

The FPGA project is to porting a WLAN’s PHY cores into a Xilinx FPGA development board (E.g Spartan 3A). Use of the public domain WLAN’s PHY cores from Rice University’s WARP project (), the cores (Matlab Simulink’s mdl files) porting into a Xilinx FPGA development board. We recommend to goto the link (above), download the matlab files, and try out yourself first before your bid. Details Project Tasks are followings; • Break the WARP’s Simulink’s mdl files into transmitter (Tx) and receiver (Rx) parts (currently, the WARP mdl files are combined) because the core logics are too big for the Spartan3A chip, and port the each part into a Xilinx’s Spartan3A-DSP board. • Perform a slight modification and adding for ...

I have the code and burnable file with me for a module. I want some one who can burn this file to specific FPGA module and post it to my place at UK. I will pay for postages as well. What I want is burning module facility. Any one be of help here?

FPGA design and architecture. More details will be discussed after reviewing resume.

I am looking for some one to make a memory that has a hold staus while memory is fetching memord ,the input pins are Adsress (32-Bits) ,Data (32-Bits) ,Read and write seprate (1 Bit each), abd for out put must have a hold output (1-Bit) which should be at logic high when memory is busy while reading.

...depending on deviation) c) FM Video demodulator with AGC and AFC output (automatic gain & automatic frequency control) d) FM Stereo audio demodulator PLL with bandpass filter ( 6.0MHz, 6.5 MHz for example) e) PAL and NTSC deemphasis switchable f) High quality video amplifier for 1Vss e) High quality stereo audio amplifier All components shall be in SMD, we can manufacture the pcb if a DSP or FPGA is used 2 pcs preprogrammed units have to be sent for testing. The hardware design and the software of the uPC must be fully documented. The design needs to meet regulatory and industry compliance requirements. You must be able to meet deadlines agreed by both parties. If you think you have the skills and time required please get in touch – this is basically ...

I'm working on a small project which implements a simple (slow) serial CPU bus in a FPGA. The CPU bus is 2 bits wide and uses a transition based protocol. The code is written in VHDL and functional but the system contains bugs. You will review my code, consult me how to improve it and try to find bugs. The code base is only a few hundred lines and is simple in nature. The bug(s) can be in the code but also in my physical setup. Communication will go through a chat application such as MSN, Google Talk, IRC (I'm open to alternatives). My timezone is GMT+2. I expect you to have a good knowledge of VHDL, Experience with Altera FPGA and the Quartus II development environment, basic to good knowledge of digital electronics. A bonus upon succesful completi...

I have an Altera DE2-115 evaluation board with a Cyclone 4 FPGA processor (EP4CE115F29C7). I need a HDL design either written in Verilog or VHDL that implements a SPI core. I want to transfer data between the FPGA evaluation board and a PIC24 microprocessor evaluation board from Microchip. The data consists only of a few bytes that are transferred in both directions approximately every second. The HDL design must be written so that i can use it directly in Quartus II software by embedding the SPI core into a top level schematic file. You should only make a bid if you are familiar with Quartus II and if you have the necessary hardware to test your SPI HDL design, or if you have so much experience with FPGA SPI that you are very confident that your design will work.

...clearly show the contributions of the various sub-tasks. The report should include at least the following items: i. a complete functional description of the system. Also include a block diagram of your synthesized design ii. a description of how the system has been mapped onto the board resources, including pin-outs and include a summary of the FPGA resources used. iii. A discussion of the simulation rationale (i.e. what you were trying to achieve) and the results – annotated in a manner that makes is completely clear that you have achieved what you set out to achieve. iv. A discussion of the results of the timing analysis. Discuss area and performance. Were there a...

I need a good example / framework for doing a custom camera driver. We'll be creating an USB camera that outputs the video data as frames through USB. To do the hardware development, we'll need a simple video driver frame. We need to be able to code the audio/video unpacking inside the driver, as we're developing the packing in the camera FPGA. The driver sample must have the following features: When a USB device with correct (TBD) VID/PID combination is connected, start the driver and open 4 connections (1in 1out for control, 1in for video data, 1in for audio data). Any commonly available device will do for an example of this part as long as the code is well commented. Mouse, Suggest a device for this part. (We'll be using Cypress FX2LP chips for USB o...

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Hello You will get $2000 if you get me a job in Saudi Arabia or in other countries as well. I am a digital design engineer with large experience in system-level design, simulation of various communication systems and digital signal processing targeting FPGA as an implementation platform. Further details can be discussed with the interested bider. Thanks Ahmed

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...lasers and high speed cameras is used there. The modern algorithms of computer vision perform into our measurement systems. We are looking for radio engineer who can operate with complicated tasks, concerned of microelectronics development. Requirements: At least 5 years of microelectronics development experience. High education (master degree desirable). Experience in video processing. FPGA skills, microcontroller skills. Good knowledge of C++. Deep knowledge of physics. Deep knowledge of mathematics, numerical methods, signals processing, well algorithmic grounding. Skills in modeling environments: Matlab - necessary, LabView – desirable. Also, it necessary that candidate has possibility to long business trips to Syktyvkar or leaving for Russia. Con...

Skills required: * Experience with Xilinx Virtex-5 or Virtex-6 FPGA * Experience with Xilinx EDK designs * Competent in VHDL Extras: * Experience with XUPV5 development board * Access to a XUPV5 development board The job is to develop a peripheral core in VHDL and a test project for EDK to verify the core on the XUPV5 board. The peripheral will use the PCI Express Endpoint internal core of the Virtex-5 FPGA and provide a user FIFO interface. The peripheral will contain a DMA scatter gather engine to enable the software in the host PC to setup DMA transfers between the host PC and the FIFOs. There will be 8 FIFOs (or channels) that can be targeted by the host software.

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I have developed an interface between PC and FPGA through Ethernet and tested by Telnet and receiving raw data at PC Now i want that Ethernet should be interface with live streaming data from camera (the video capturing from camera is already achieved and data is saved in external memory ) so that i can save the video capture from camera in PC Basically it is required to interface two models i.e video capture model which take camera input and Ethernet model so that data can be sent to PC i have used Xilinx Platform Stdio (10.1) The job should be completed is 5 to 6 days maximum...

Iam doing compression on fpga .I have created a 8x8 motion jpeg compression core and its simulation is oky (working correctly in ISE) but it is giving me problem in fpga which is to be sorted out and should be corrected 2nd i have created a model which take input from camera and saves video in external memory and displays on projector (tested i.e working correctly) 3rd i have made another model which interface the ethernet of Kit with testing purpose i have send a video through matlab to fpga ,saved in external memory and received back on PC(the program is working correctly) Now the task is to first correct the core and then integrate all these model to get final product FINAL PRODUCT: input from camera compression is done and outputs through ethernet and save ...

I am the moderator of 2 linkedin groups which needs to have logos. The one is "ARM FPGA" with focus on ARM processor and FPGA (such as Actel's SmartFusion etc.) The second one is "Linux Home Automation" with focus on Linux based home automation products. I need 2 logos for these groups, nothing fancy, something simple.

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USB 3.0 driver circuit design FPGA coding PCB layout

I Have done video capturing on xilinix following task has to be done 1 video compression 2 video decompression or use a pc to decode the compressed video Time line 40 days

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... The project is to create a carrier board similar to the Gumstix Tobi but with additional functions. The carrier board is for the Gumstix Overo FE computer module. The initial phase is to have the carrier board include : Power regulation (PTN7800WAH) 10/100 Ethernet (LAN9221) 10/100/1000 Gig Ethernet to USB (LAN7500) Super Cap backup voltage for Gumstix RTC Spartan6 16LX/25LX FPGA on the Gumstix's expansion bus Additional Audio Codec (TLV320AIC3254) + PA Serial Ports (RS232/RS485 via MAX3160) LCD port to 1.4" x 1.4" OLED (Sparkfun LCD-09678) Accelerometer (ADIS16240) JTAG header microSD slot (Molex 500901-0801) Dual 2mm Samtec (40 positions) for I/O and power position along the narrow edges of the board. The PCB is expected to be 4 or ...

...freelancer. The project is to create a carrier board similar to the Gumstix Tobi but with additional functions. The carrier board is for the Gumstix Overo FE computer module. The initial phase is to have the carrier board include : Power regulation (PTN7800WAH) 10/100 Ethernet (LAN9221) 10/100/1000 Gig Ethernet to USB (LAN7500) Super Cap backup voltage for Gumstix RTC Spartan6 16LX/25LX FPGA on the Gumstix's expansion bus Additional Audio Codec (TLV320AIC3254) + PA Serial Ports (RS232/RS485 via MAX3160) LCD port to 1.4" x 1.4" OLED (Sparkfun LCD-09678) Accelerometer (ADIS16240) JTAG header microSD slot (Molex 500901-0801) Dual 2mm Samtec (40 positions) for I/O and power position along the narrow edges of the board. The PCB is expected to ...

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I have a Win CE 5 application that is written for ARM9 CPU running an industrial machine. the application is divided into 2 parts: 1 /. GUI that respond to buttons 2. Communication (DLL) that communicates with BL layer that is implemented on an FPGA. a new hardware is created that has all BL within the application so the FPGA is removed. the tasks are: 1. GUI is untouched 2. Code redesign 3. remove communication code 4. add BL into the application 5. write drivers (SPI, I2C,UART). some of this is provided by the vendor but some adaptations are needed. 6. upgrade to wince 6 Please respond ONLY if you have good experience with WinCE.

Zlecenie polega na uproszczeniu projektu demonstracyjnego w Quartusie 9.1. Należy usunąć zbędne elementy oraz okomentować kod. Proszę licytować koszt wykonania tych czynności, w komentarzu dodatkowo proszę podać cenę "konsultacji" za godzinę.

...that softcore procesor on FPGA to run an application program (edge detection algorithm : sobel edge detection). i want to do real time video processing using FPGA. i want the code to be written in either VHDL or C. the design of softcore processor is similar to the tutiorial given in the altera website under name"introduction to SOPC builder using VHDL" ## Deliverables 1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright ramifications are explained AND AGREED TO by the employer on the site per the worker's Worker Legal Agreement). i want the project in running condition. i want to coder...

Development of a PID controller in HDL (VHLD or Verilog) for Xilinx FPGA Spartan 6. The development shall be with WEBPACK Xilinx. The? implemented PID shall not be larger than 400 slices. The The PID shall be developed? at 32bits precision, and intermendiate values extended at 48 bits and shall include: • command ??" The setpoint, as commanded. • feedback ??" as measured by a feedback device. • output ??" The elaborated output command that is the control signal . • error ??" is command minus feedback. • enable ??" A bit enabling the PID. If false, all integrators are reset, and the output is forced to zero. If true, the loop operates normally. The PID gains, limits, and other ’tunable’ features of the loo...

I need information on all FPGA, CPLD and ASIC chips from the internet. The information should be returned in .xls format. There information's required r name, origin, technical info's like, clock speed, number of pins, number of reconfigurable gates and all other technical info's that is available on the internet. There r few chips of these kinds online, so it wouldn't be a tough and lengthy job. Please bid who can complete it within 3 days. Daily update is required. For more info just send me a message. Imon ## Deliverables 1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright ramifications are ...

There is a requirement based on P-SOC/FPGA with following details. 1. The system should have following interfaces: a. USB b. PCMCIA c. RS-422 d. ARINC-717 e. ethernet 2. The system should be able to acquire data on RS-422 & ARINC-717 interface. 3. The system should then be able to store the data in to an external memory(256 MB) & PCMCIA card. 4. The system should be able to retrieve the stored data using USB and ethernet interface.

i want to implement softcore processor NIOS 11 on FPGA. i need the code for this to run on FPGA. ## Deliverables 1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright ramifications are explained AND AGREED TO by the employer on the site per the worker's Worker Legal Agreement). ## Platform quartus ii 9.1

Project: Ethernet Hub/Repeater on FPGA Ethernet: 10/100 Base, Opencore IP Connection: 2 IP Core + Host Languages required: HDLs (Verilog, VHDL), HVLs (Tcl, Perl), C Required skills: Ethernet, FPGA design - If this work is successful, I have more project to work together. - Compensation is based on your contribution. We will work together, and I can handle all. But, I may expect at least around 50% contribution, sorry not for entry level. - Local (Toronto Canada) preferred, but not mandatory.

Verilog design and testing skills

The FPGA project is to porting a WLAN’s PHY cores into a Xilinx FPGA development board (E.g Spartan 3A). Use of the public domain WLAN’s PHY cores from Rice University’s WARP project (), the cores (Matlab Simulink’s mdl files) porting into a Xilinx FPGA development board. We recommend to goto the link (above), download the matlab files, and try out yourself first before your bid. Details Project Tasks are followings; • Break the WARP’s Simulink’s mdl files into transmitter (Tx) and receiver (Rx) parts (currently, the WARP mdl files are combined) because the core logics are too big for the Spartan3A chip, and port the each part into a Xilinx’s Spartan3A-DSP board. • Perform a slight modification and adding for ...

Develop the firmware for FPGA board that acts as converter between CPRI optical links and SRIO buses, based on off-the-shelf IP cores for CPRI and SRIO. Delivery includes code with full working and tested implementation.

Need to design a FPGA Temperature monitoring system using VHDL. The target board used is a Spartan 3A starters development kit. Temperature sensor is a K-type thermocouple connected via the RS232 port. Refer Sensor circuit attached. Readings should be displayed in the onboard LCD of the target board.

...(architecture design and coding in VHDL). I have no prior experience in this field. Can you help me out. I have given a short note on my project below. I have to design a barrel processor that has to execute only one instruction from each thread at a time for all threads upto N threads. I need to design the architecture for the Barrel processor and has to implement the processor on a FPGA by using VHDL. So, I have to take a basic architecture of any of the processor and have to modify it such that the processor has N - number of PC,SP,SR,Thread IDs,etc. for each thread. I have to cycle all these registers of each thread at their turn executing only one instruction at a time. For example Thread -1 is taken and all its corresponding CPU registers...

I need simple solution for analog-to-digital conversion using the Xilinx Spartan 3E FPGA and the onboard A/D converter on Xilinx Spartan 3E Starter Kit development board. I need to sample signals on 2 channels of the A/D converter with the sampling frequency of about 1.5 MHz. The solution should be developed as an vhdl-module.

I need an Electronics Engineer with good experience in VHDL programming, PCI board design, DMA. The deliverables are schematics, gerbers, and BOM.

...You should have extensive knowledge and experience in developing and testing WiMAX MAC with WiMAX baseband radio. We have a WiMAX BB ready and we will need you to make our existing MAC lab and field ready. We will furnish a development platform containing the Virtex 5 SX50 ( or SX95) FPGA, an Xscale PXA270 processor, and the baseband radio. There is a JTAG connection for the FPGA. The processor contains a full Linux OS and has drivers for loading the FPGA bitmap file, and communicating between the FPGA and Xscale over the external memory bus. There are APIs contained in the Xscale for operating the radio including frequency tuning T/R switching, gain control, etc and there is also an Ethernet connection that will permit transferring in new bitmap files, ...

I want to build an audio chain taking audio in from an analog mic into the Stratix board, perform the appropriate processing and transfer into a buffer for on demand use by the host system over USB. Stratix II has line in, ADC, FPGA and output buffer. I have run the processing in MatLab but have not built the H/W model(s) that can be either used by Quartus or transferred from Simulink to Quartus. I have Quartus running on my workstation but don’t know that much about using it. I have built a demo model (counter) in Quartus II to verify everything is working (including me) but the Quartus S/W does not see the USB Blaster to program the board. I’m presently debugging this, waiting for help from Altera. What I would like to have: Someone who knows enough about Altera tools ...