Fpgaεργασίες

Παρακαλούμε Κάνε Εγγραφή ή Κάνε Είσοδο για να δεις λεπτομέρειες.

...days, local server time, current BTC network difficulty, The Block number that the pool is currently working on, Report on how far past 10 minutes the last block found on the network, Server "Luck", blocks found by the pool in the past, Records of the payouts on each block found. 18. Identify the type of chip that is connecting to the pool so that stats can be made on which types of miners (CPU,GPU,FPGA or ASIC) are working on the pool with the option to show which type of chip has solved x number of blocks. 19. Pool stats should be dynamic so that they show miners their potential payout page to give active miners an idea of what their payout would be if a block was to be found at that time. 20. Pool source code built will be exclusively used for this project and not sh...

Devlop a model to detect skin cancer using conditional GAN translation and apply on cnn models. Execute the model on fpga processor

I want someone who understands FPGA, Vivado, Verilog, VHDL etc for a report

QPSK modulation and demodulation with Turbo Encoder/Decoder, Interlever, Channel Estimator, Channel Equalizer, Pulse shaping filter, coarse and fine synchronization etc. Defined Parameters: Data Rate: 16kbps, 100kbps, 2msps Modulation Scheme: QPSK Bandwidth: 25KHz, 300KHz, 2MHz Sampling Rate: Twice of Data Rate Software: Vivado 2019.1 (for hardware design d...Channel Equalizer, Pulse shaping filter, coarse and fine synchronization etc. Defined Parameters: Data Rate: 16kbps, 100kbps, 2msps Modulation Scheme: QPSK Bandwidth: 25KHz, 300KHz, 2MHz Sampling Rate: Twice of Data Rate Software: Vivado 2019.1 (for hardware design development) on Zynq 7035 and 7030. Linux Based OS to make Linux OS executable files. Hardware: Zynq 7030 and 7035 FPGA and AD9361 Tr...

To interface lattice FPGA with ultrasonic sensor (5 )and lidar sensor(4) with the provision for connecting an MIPI based camera module (no AI stuffs),the FPGA would be connected to stm32h7 via SPI interface . More details via chat including the sensor type

...local server time, current BTC network difficulty, The Block number that the pool is currently working on, Report on how far past 10 minutes the last block found on the network, Server "Luck", blocks found by the pool in the past, Records of the payouts on each block found. 18. Identify the type of "chip" that is connecting to the pool so that stats can be made on which types of miners (CPU,GPU,FPGA or ASIC) are working on the pool with the option to show which type of chip has solved x number of blocks. 19. Pool stats should be dynamic so that they show miners their potential payout page to give active miners an idea of what their payout would be if a block was to be found at that time. 20. Pool source code built will be exclusively used for this project and ...

Looking for FPGA developer to write simple program on Intel Stratix board

completing design demonstration of work and explanation Report and final work -this includes all the recording of work -how and why

Devlop a model to detec skin cancer

Hi, How are you doing. I am looking for electrical engineers to work on multiple tasks in following areas: • Embedded C Programming. • VHDL/Verilog, LABView/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. I am looking for long term work relationship. New freelancers are warmly welcomed. Important Note: I need dedicated freelancers who strictly follow the deadline and give me good quality work without any plagiarism.

Looking for an experienced designer / electrical engineer to move further with our products. We currently have 4 projects that involve ESP32, FPGA and MPUs. We're hoping to find someone who will be able to work on our other projects after completion of the first one. This particular project involves a 4 single layer board design using ESP32, solar power management, super capacitors and SPI display. We're looking for someone who is able to complete the project based on the requirements and is able to provide consultation on the future designs.

Hello,I am looking for guys who could integrate the AD9361 with lattice FPGA series and also port some of the codes which were made fro the xilinx FPGA into the same lattice FPGA.

Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

We have a need for a programmer for both microcontrollers and FPGAs to control I/O from a host computer to custom high channel count, high voltage drive electronics used to control deformable mirrors.

accept digital RGB input (24bit + HS VS DE) in one resolution, output digital RGB output (24bit + HS VS DE) in another resolution. Features required : 1. optional de-interlacer (swit...source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed memory interfaces signals to the memory multiplexer. Any dev board and any FPGA device can be used for testing it on. It is essential that the potential developer will provide the samples (with code fragments) of previous experience. More than 3 years of Verliog/ HDL experience ...

we have to give input images for that it should create a eigen face by using eigen values and eigen vectors and compare it with the given image matching or not in verilog so that I wanted to implement in the FPGA board I want it in gate level model

We need to develop a GUI in a preact framework, using Javascript, interfacing to an FPGA via a FTDI chip over USB. I uploaded the mock up code we have running, showing some details in what we have thought. Base code is to be in GO.

I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.

The objective is to create a verilog code for image dehazing. The image is converted into a text file using Matlab(all pixel values are converted into corresponding hexadecimal values). This text file is given as the input to the verilog program. First we need to find the minimum of RGB value of each pixel and create a matrix. Then we need to consider a small window/mask in the new m...the entire new matrix to create the darkchannel image. Then by using the equations using the darkchannel prior algorithm we need to recreate a haze free image. (the output of the verilog code will be a text file and is recreated into an image using Matlab. I am attaching a reference paper. I just need to get the basic dehazing part from it. #verilog #matlab #imageprocessing #darkchannelprior #fpga...

I need code for my bot who follow the given line using line sensor. this code should be written in verilog language and fpga cyclone 4 is used as board.

We are in the need of FPGA Engineer for a SDR product. We want to maximize the Power Output of SDR (Software Defined Radio) with the use of Amplifiers. You can have remote access to customize the FPGA of the SDR + Amplifiers. Currently we have them already operational - however, we know that we need to tweak more to maximize this. No need to fully re-write the FPGA coding - it is truly tweaking the code based upon Technical Git / Manual information. Budget 500 - 750.

Input(Live video) is accessed from the camera connected to the board and output should be displayed in the monitor connected to the FPGA board. and output should have a bounding box with a label of the detected object.

In this project students are asked to implement a an XTEA Encryption/Decryption VHDL Engine, implemented in both C code and VHDL code. It supposed to be built as a custom hardware module and be interfaced to the NIOS II soft processor in the Alter- Intel Cyclone V FPGA chip [De-10Nano board]. The HDL code implements 2 number of pins: first an input from stdr_logic_vector type form of 32-bit length, and second an output with 32-bit of the same type. The Key is 32-bit in length, and they must be stored inside the VHDL code. The input reception and output generation may take multiple clock cycles or states but could be designed in less than that if was applicable. The internet could be surfed to lookup codes for both C and VHDL but the group is responsible to convert and modify the cod...

Hi I need a expert in red pitaya.I want to design project using red pitaya

We need a VHDL designer with expertise on video processing codec.

We need a script to automate our FPGA design flow. Preferred in tcl language 1. Set the environment 2. Grab sources from repo 3. Run simulation and regression test 4. Run synthesis and place and route (vendor independent) 5. Generate reports 6. More than one project, we want to run it during night time

the company needs FPGA design services support for a multichannel DMA systes

I need to use Xilinx IIC IP on Artix board as a master, I used it in master mode and it didn't work well (The generated signal seems to be random) I tried the IP on Zynq platform and it worked well, but on Artix it beahves inproperly! I need someone to get it up and running on my chip.

Xilinx ZCU104 MPSOC FPGA Expert

Im working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM

Im working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM

Objectives of this project are Benchmarking speed, ROM, and RAM usage of software implementations of Simon and Speck's ciphers using C++ and XILINX to improve the performance of SIMON and SPECK on ASICs, FPGAs, microcontrollers, and microprocessors. - Memory benchmarking via C code - Slice count benchmarking via FPGA - Gate equivalent benchmarking via ASIC Implementation

We are a high frequency trading startup based out of India and we are looking to setup an fpga based trading infrastructure

We are a high frequency trading startup based out of India and we are looking to setup an fpga based trading infrastructure.

Objectives of this project are Benchmarking speed, ROM, and RAM usage of software implementations of Simon and Speck's ciphers using C++ and XILINX to improve the performance of SIMON and SPECK on ASICs, FPGAs, microcontrollers, and microprocessors. - Memory benchmarking via C code - Slice count benchmarking via FPGA - Gate equivalent benchmarking via ASIC Implementation

Hi James P., I wanted to ask if you are busy with other projects now? I have a new project I need help with and I can give you more details next week but it basically revolves around the Mister FPGA, a gaming setup and that I need help with creating some add-on boards. Thanks, Per C.

Hi Jacob V., I wanted to ask if you are busy with other projects now? I have a new project I need help with and I can give you more details next week. The project is about making some external pcbs for something called Mister FPGA system, maybe you know what it is?

Hello guys, I am looking for skilled FPGA programmer who could implement machine learning (object detection & classification) of tiny metal objects etc on a FPGA SOM module. The FPGA will detect object using data from high resolution camera's (not less than 720P) usb port/camera interface,lidar module (atleast 6 sensor) & ultrasonic sensor module (atleast 7 sensor) i2c line and will be connected to servo motor and BLDC motor ESC. The FPGA should output in low latency H.264/H.265 format with AES 256 encryption/similar. More details will be revealed via chat. The freelancer is free to choose an ideal cost effective FPGA SoM module for this task. Please don't apply if you can't complete the task or unsure about your capacity ...

We need to program a FPGA board using verilog code with XNOR, Multiply, shiftleft and add modules that can run on the board using different switches. When we compile the code there are no errors but when we try to put the code onto the board it is showing only zeros so we think that there is something wrong with the XNOR, Mul, shiftleft or ADD modules. I will attach all codes and the manual for the project below, thanks.

Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

I need help in Machine code for MIPS processor to design pipelined processor with FPGA support. Detailed analysis and research is required

I need to implement digital signature algorithm in Xilinx Vivado Design Suite using Verilog. Please find the attachment for complete details of project.

I want to create programming routines to be recorded on an FPGA

Project to be done in VHDL, so I am looking for an expert. The objective is to create a testbench for one circuit, and simulate the a few operations including storing data in it as well as retrieving data from it. I can share more details in PM.

Project to be done in VHDL, so I am looking for an expert. The objective is to create a testbench for one circuit, and simulate the a few operations including storing data in it as well as retrieving data from it. I can share more details in PM.

I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.

Hi Mohammed Ibrahim, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

Hi Mohammed Ibrahim, I noticed your profile and would like to offer you my project. We can discuss any details over chat.