Need to implement different logics using primitives like IDELAYE3 / ODELAYE3 primitives to calculate delays accurately with few PS resolution.
Hi, i have this coding about image processing using verilog that i took from here [κάνε είσοδο για να δεις το URL] but i have a problem trying to make it synthesizable. Can you help me with that?
Hello, I have an accelerometer (I2C) and I want to read it and print the output on the terminal through UART. The code must be written in Verilog or SystemVerilog targeting Xilinx FPGAs. It will be tested in a Digilent Cmod A7. Design: I2C Master <-> FSM <-> UART
I need someone who can Implement optimized bitsteam for both card types cvp13 as well as bcu1525 .As well as DNA locked pc [κάνε είσοδο για να δεις το URL] file. It should be a Bitsteam and miner application for both cvp13 and bcu1525. Kawpow algorithm minimum hashrate of 400mh for...
I have a verilog model for DLL and the model needs to modify it based on some requirements. This is simple task for the one who has a good background in this context but you will get benifit from continuing with me in this project
- Comparing and analysis the performance of existing protocols such as Epidemic, Spray and Wait and PROPHET using ONE Simulator - Required to design and create new routing protocol based on existing protocols such as Epidemic, Spray and Wait and PROPHET protocols using ONE Simulator. - Implement and simulate the new routing protocol using ONE Simulator
Searching for someone with experience in Vitis AI and various HLS optimization techniques. Please leave your hourly rate and experience with Vitis AI. Memory access and computation optimization.
Anyone interest in building FPGA to mine bitcoin or other type of crypto currencies.
The LimeSDR-USB allows to either transmit signals at once or schedule them. In all cases the samples must be passed from the host to the device at each call, which can take time due to the USB speed and latency. We would like to be able to just tell the device to transmit a specific type of signal, either at once or at a specific timestamp, without passing the samples each time. The different sig...
deadline: 8 hours project is about optimal power flow using barnacles mating optimizer with applied matpower in case IEEE 30 bus.., I want you fix my opf coding to get the result fuel cost and power loss.., and the relate my algorithm to matpower toolbox.., for matpower, i use case_ieee30, that's all, and also in the result i want keep power output for generator, bus voltage, shunt capacito...
Write 16 bit RISC processor verilog code and test bench code in structural programming. Explain the working of the code. Write a report of the project too. Don't write code in behavioral programming. Preferred software (ISE PROJECT NAVIGATOR)