Hi, glad to bid on your project. I have read your description,
Experience on VLSI with VHDL , Verilog , Spice , system Verilog. Xilinx Qurtus Casance
I m a Doctorate in Engineering ,i have a 18+ years of experience on research & development papers solutions with teaching
I want to discuss the project further with you. waiting for a reply from your side thanks.