Computer Architecture

Q1. Suppose that your processor has 4MB data cache and its block size is 64B. Physical address to access the memory is 52-bit wide (addr[51:0]). For each of the following cache structures, calculate TAG size. a) A direct-mapped cache implementation b) A 4-Way set associative cache implementation c) A fully associative cache implementation Q2. The following memory addresses are used consecutively by a running program (from left to right) (20 points) 2, 5, 6, 9, 21, 18, 20, 57, 10, 11, 5, 43, 6, 7, 10, 18 In each of the following Cache Structures, compute the number of hits, misses and the final value of each stored in each cache location. Each word is 1-byte. (a) Direct-mapped cache with four-word blocks and a total size of 16 words. (b) Fully-associative cache with four-word blocks and a total size of 16 words. (LRU replacement) Q3. Write a program to emulate the behavior of uniprocessor cache in any programming language of your choice (C++ or Java). The program gets the following parameters as input: BS: Cache block size (e.g. 8 means each block includes 8 words) CB: Number of cache blocks MMB: Number of main memory blocks WS: Size of each word in terms of bytes (e.g. 4 means that each word includes 4 bytes) AS: Associativity (Value of \\\\\\\'1\\\\\\\' denotes a direct mapped cache. Value of \\\\\\\'2\\\\\\\' denotes to 2-way set associative cache and 4 denotes to fully associative cache). AT: A sequence of memory address. Note that LRU method is used for cache replacement of fully-associative and set associative caches. You may need to maintain the status of how recently each block was used in a \\\\\"status array\\\\\" of usage of cache data. You can use this program to verify your answers to Question2. Note: 1- You should show the details for each questions (show steps). 2- without any plagiarism.