Hello,
I need a VHDL design which converts the complete DDR3 SDRAM Memory to a 5-Bit FIFO.
The target Memory is Micron MT47H32M16HR -25 or -3 speed grade.
Target FPGA is Xilinx Spartan 6 XC6SLX9-2CSG324C.
Design should work in Xilinx ISE 14.7 Simulator.
Attached is the TOP VHDL file to give an idea how it looks like.