RS-FEC 198,194 verilog code
$30-250 USD
Πληρώθηκε κατά την παράδοση
VLSI design for Reed Solomon FEC for 198,194 including documentation and explanation.
Verilog files and simple testbench to prove the design.
ASIC
Ταυτότητα Εργασίας: #20012622
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Hi! I believe I understand what you need. I have done several Verilog/VHDL design projects which are either implemented in FPGA (Xilinx and Lattice) or ASIC for the past 10 years. In fact, I already implemented the Περισσότερα
8 freelancers κάνουν προσφορές κατά μέσο όρο $110 για αυτή τη δουλειά
Hi my Professional Aim is: ( Services then Solutions then Satisfactions) I hope you are good. As an experience in this field from last 5 years i am sure i can do it perfectly with in a time a Περισσότερα
I have well experienced in doing such kind of jobs........................................................................................................................................................................ Περισσότερα
Hello! I have briefly read the description on fec-verilog-code development project, and I can deliver as per the requirements however I need us to discuss for more clarity on the details, deadline and budget as Περισσότερα
Hi, I have worked on Verilog, VHDL, System Verilog and have developed many complex IPs for FPGA and ASICs. I can develop this verilog code for you. Let me know whether you are looking for an encoder only. Also shar Περισσότερα
Hello sir, i am girish Phalake, FPGA design engineer with better industry experience, i am very good at paper design and also good in english Thank you!
I have well experienced in the following topics.. Electronic circuits,Digital electronics Signals and system,Digital signal processing Digital image processing,Verilog/VHD Περισσότερα
