Luv Y.

I am a Goal-Oriented Senior Digital ASIC/FPGA Engineer with 13+ years of experience. Several work experience enable me to pick up and own new concepts to contribute with innovative work. Profiency in UART,SPI,I2C,etc interface. Verilog -- Reliable and efficient code for simulation and synthesis, mainly for Xilinx and Altera FPGAs. Also with experience in writing Verilog for ASIC. High awareness of device targetting in source code. Careful and secure clock domain crossings. Perl/tcl/Make -- familiarity with the language,can write simple script to enhance the work efficiency Circuit Board -- work closely with Hardware Design Engineer to discuss the system design.