Εικόνα προφίλ του/της loi09dt1
@loi09dt1
Flag of Singapore Singapore, Singapore
Member since 10 Αυγούστου 2014
29 Προτάσεις

loi09dt1

Συνδεδεμένος Αποσυνδεδεμένος
An experienced FPGA/Verilog/VHDL Engineer with more than 6 years experience and hundreds of FPGA projects in Verilog/ VHDL, Digital Logic/Circuit/System Design in LogiSim/CEDAR, and MIPS Assembly. Also a Verilog/VHDL Codementor and Founder of FPGA4student. Expertise: Xilinx ISE, XPS, EDK, SDK, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, Qtspim, MARS, PSpice, Altium, OrCAD, Proteus, Arduino. - Featured FPGA projects: + Video/Image Processing on FPGA: FPGA/Verilog/VHDL Implementation of Gesture Recognition/License Plate Recognition, Fingerprint Identification, Image Compression in Wavelet Domain using DWT and SPIHT, Image Enhancements including Noise Filtering. + Fixed-point and Floating Point FPGA projects in Verilog/VHDL + AES, SHA 128, 192, 256 Implementations on FPGA + OFDM Transmitter/Receiver, Signal Generator on FPGA + Single/ Multicycle/ Pipelined RISC/MIPS Processors in Verilog/VHDL/Logisim + Games on FPGA and many other FPGA/Verilog/VHDL projects
$50 USD/hr
173 αξιολογήσεις
6.8
  • 98%Ολοκληρωμένες Εργασίες
  • 92%Εντός Προϋπολογισμού
  • 97%Εντός χρόνου
  • 14%Βαθμός Επαναπρόσληψης

Δείγμα Δουλειάς

Πρόσφατες Αξιολογήσεις

Εμπειρία

FPGA/Verilog/VHDL Developers

Jan 2018

Founder of FPGA4student. An experienced FPGA/Verilog/VHDL Engineer with more than 6 years experience and hundreds of FPGA projects in Verilog/ VHDL, Digital Logic/Circuit/System Design in LogiSim/CEDAR, and MIPS Assembly. Expertise: Xilinx ISE, Vivado, Quartus, Modelsim, Logisim, CEDAR, Qtspim, MARS, PSpice, Altium, OrCAD, Proteus, Arduino.

Founder

Nov 2016

FPGA4student where shares free FPGA/Verilog/VHDL source code/ projects/ tutorials with EEE students. Also offering FPGA/Verilog/VHDL Design/ Tutoring/ Consulting Services.

Researcher

Sep 2014 - Dec 2014 (3 months)

VLSI/Verilog Implementation

Experienced FPGA/Verilog/VHDL Engineer

Aug 2014

An experienced FPGA/Verilog/VHDL engineer with more than 6 years experiences on FPGA Design using Verilog/ VHDL, digital logic design LogiSim, Circuit design, MIPS Assembly, etc.

Internship Student

Oct 2013 - Feb 2014 (4 months)

ASIC Design

Internship Student

Jun 2012 - Aug 2012 (2 months)

Microcontroller and Embedded Programming

Εκπαίδευση

Bachelor of Engineering

2009 - 2014 (5 years)

IC Design Course

2013 - 2014 (1 year)

Qualifications

Certificate of Merit (2010)

Danang University of Technology

Best students in class

Intel Vietnam Engineering scholarship (2012)

Intel Vietnam

Scholarship for top engineering students at DUT in 2011 and 2012

Odon Vallet scholarship (2013)

Prof. Odon Vallet and "Meeting Vietnam" Organization

Scholarship for best performed students in central region of Vietnam in 2013

IC Design Course Completion (2014)

Synopsys

IC Design Course using Synopsys Design Tools

Δημοσιεύσεις

A FPGA-Based Embedded Fingerprint Identification System

A FPGA-Based Embedded Fingerprint Identification System

A FPGA-Based Embedded Fingerprint Identification System

A FPGA-Based Embedded Fingerprint Identification System on the 2014 National Conference on Electronics, Communications and Information Technology – REV-ECIT 2014

Πιστοποιήσεις

  • Preferred Freelancer Program SLA
    97%
  • Numeracy 1
    94%
  • Digital Electronics Level 1
    88%
  • Analog Electronics Level 1
    83%
  • UK English 1
    80%
  • US English Level 1
    75%

Επαληθεύσεις

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