Reproduce an Vhdl Testbench in UVM
€12-18 EUR / ώρα
I need one UVM verification engineer to help me building an UVM testbench to enhance the verification of an vhdl IP. An vhdl testbench already exists and can be used to start with.
Looking to hear from you.
regards,
Ταυτότητα Εργασίας: #22470439
Σχετικά με την εργασία
6 freelancers κάνουν προσφορά κατά μέσο όρο €16/ώρα για αυτή τη δουλειά
Hello, i have read the details provided..please contact me to discuss more on the project deadline and some other few things
Hello Dear Concern, We are a team of professional members of Electrical, Electronics, Mechanical, Civil, Chemical, Energy, Industrial Engineering. We are also expert in following softwares: VERILOG, FPGA, MATLAB, Simu Περισσότερα
Hi, I'm ready to start your project. could you share your design overview, what time line do you have? Using already existing TB will decrease time to finish UVM verification environment.
Hi, I am an ASIC Design Verification Engineer with 4 yrs in Verilog IP design, and 4 yrs in Verification (3 yrs verification in eLanguage - Specman, and a year in System Verilog UVM). Best regards Relevant Skills an Περισσότερα
I am a professional Electrical Engineer with 10 years specialization in Control Systems (Linear and Nonlinear Control Systems). I Specialise in Control System & Unmanned Ae Περισσότερα
I am a trained VLSI front end engineer with skill sets including Verilog,System Verilog and UVM . I think my skills are in alignment with your requirements. Looking forward to connect with you. Relevant Skills and Exp Περισσότερα
