Develop a 44 multiplier. The multiplier uses a shift and add algorithm. The multiplier uses 2
phase clocking system
The inputs for the multiplier are A (A3, A2, A1, A0) and B (B3, B2, B1, B0), Reset and Start.
The outputs for the multiplier are O (O7, O6, O5, O4, O3, O2, O1, O0), and Finish
The operation of the multiplier is as follows
1. When Reset = 1 the system is reset
2. When start = 1 the following occurs
a. Load A on the first 1
b. Load B on the first 1
c. After n cycles the output is stored in O and the Finish output is asserted
d. There is no change to the output after subsequent cycles.
In this phase you are to describe the HDL code that you will use and the specify the names and timing types
(s1, s2, etc) for all signals used to implement the system
Prepare a well organized and well written report that describes your analysis, model development, and
simulation results.
I am a communications and electronics engineer and I am studying for an MSC. now. I guarantee your privacy and my accuracy. I hope I can satisfy you. Thanks.
Hello,
For all my experience you can go to my profile and see that i have done number of project on magic VLSI like 8 bit ALU. I have very good expertise in this software. I will be able to complete this project in 24 hours.
I have already designed 4*4 multiplexer two times and i can quickly complete it and submit well professional report. Let me know if you want to see my previous design in magic vlsi.
For more information or further discussion we can talk on personal message.