FPGA Designing

Dear sir I have more than 10 years experience in FPGA design, please message me so that we can discuss more details about the required work Best regards

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

Hi there, Thanks for the invitation. I have worked in numerous FPGA projects. Kindly contact me for further discussion

I have long experience with FPGA and VHDL . I work with both intel and Xilinx FPGAs , SoC and SOPC. I use Quartus II and Vivado IDEs accordingly. I test timing compliance through timing analysis . I deliver tested , neat and well-commented code that can be reused or modified for future development. More to be discussed once you contact me . BR, M.T.

Hi, I hope you are doing well and enjoying digital design. Throughout my 2+ years of experience in the field, I had the joy of designing and implementing a part of LTE's physical layer right from the Matlab model, through RTL coding, simulations, and back-end stages. I also built many other designs such as a MIPS processor design, Can satellite, and a UART transmitter and receiver. All my designs were verified successfully on either Xilinx's Spartan S6, S3, or Altera's Cyclone V FPGA. I would love to hear your thoughts and requirements for the delivery as well. I wish you get the best out of this project. - Eslam

Thank you for your invitation, please send me more information about your project via message box. Best regards.

Let's discuss the project details. I would like to work on your project, but before we both work together , i need to know the details of your project. I shall be waiting for your prompt response.

Hello, I'm ready to start to work on your task, please share the details of the project. I mostly work on Verilog language.

I am Tawfeeq Hasan Khan, an independent embedded systems hardware enthusiast, with experience on ATMEL micro-controllers and Intel FPGAs. I am into Chip planning, Placement and Routing algorithms for Intel's FPGA chips. Currently understanding the working and capability of Nios II Embedded Softcore Processor based system design on Intel FPGAs, and my aim is to unravel the beauty of interfacing it to provide aid to the existing technologies. I like to try things that seem impossible. And by dedicated efforts, those dreams are realized.

I am an experienced designer. I have done many FPGA designs and I can do this. Please check google scholar for my credentials.