ASIC soc design Verification

i have 2.5+ year experience in design and verification, i have done 25+ project in verilog and 3+ bigger projects in SV/UVM, you can check on profile... i will done your project perfectly and on time, i will provide Περισσότερα

hi, I have a working knowledge of SV, UVM. with projects under my belt. will be happy to help you with this verification process of the design.

Hi, My name is Anjana and I am trained engineer in VLSI with good hands-on experience in Verilog ,System-Verilog and uvm. I think my skills match your requirements. Looking forward to getting connected. Regards Anja Περισσότερα

I have good understanding of digital design and can work efficiently. I have completed my masters in VLSI design and currently working in verification domain. Do contact me for further details. 9.6.8.8.5.7.1.7.5.5

System verilog +UVM team here with extensive exposure in verification. Hands-on with Oops, C++ too. Team worked for International Projects. Let's have quick chat and take this forward. Please feel free to get in touch Περισσότερα

You can say I am beginner to SV verification and design. Currently I am taking a 9 month training course under SiFive China which is going to end next month. I am doing great in my training projects. I have done 1 ve Περισσότερα

I'm keen interest in this gig. I have years of experience in FPGA prototyping, Pre & post silicon verification and validation and believe me, I can do it beautifully. I can work for about 2 hours a day and maximum 10 h Περισσότερα

I have 2 years experience in Verification job. I am good at SV/UVM and Coverage Driven Verification methodology.

I am vlsi design and verification engineer, i have done several project on Verilog, FPGA and various verification project using systemverilog and UVM.