Digital System Course HW -- 2

A proposal has not yet been provided

Hello! I can help you right away! I have 8 years experience in writing vhdl for fpga! I am also a digital design engineer! Please send me your requirements! And I will help you right away! Have a nice day!

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Hi, I am a professional Verilog HDL and VHDL developer with 15+ years of experience. Please consider my proposal for excellent, top-notch work!

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I will make it look like done by written by a sharp beginner like its written by yourself and comment the code with proper comments. I have quite enough verilog experience. hoping for a positive response

Dear! I have three years experience in ASIC field, good command in RTL design and coding with Verilog. I've been working for Dolphin Technology Inc (at San Jose, CA) since I graduated. Currently I'm designing RTL for PCI-Express controller core for my company. I think I'm a suitable candidate for your project. Thank you for your consideration and waiting to hear from you.

hello ....................................... let me know the details . thanx ............................... waiting for your response ......................... regards ..........................

A proposal has not yet been provided

A proposal has not yet been provided

I have an digital IC designer and working on HDLs (VHDL and Verilog). I can handle this job easily in an excellent way. It is quaranteed!

Hi, I am an electronics engineer with Master's degree in VLSI Design. Your project description sounds interesting. Pleas consider me for this project. Feel free to message me if you require any clarifications. Regards, Robin

First of all, I would say that I just believe in myself. Secondly, I have some good academic records and have good command in Verilog. I have just finished my final year thesis. I am in good touch. and above all....I have been working on this language since last two years. and published couple of papers also. One paper is selected in IEEE digital library and...one is having scopus index.

If you could share the problem, it would be really great. However my expertise in Verilog is good enough for any problem.

Hi, I am currently working as a RTL design engineer and have very good understanding of Verilog HDL. Since I have practically desing many circuit using verilog HDL. Good knowledge of simulation friendly , timing friendly , RTL design. Please contact me for futher discussion. Thanks sagar