Develop TLM model of some embedded system + implementation on ZYNQ Z-7020
$30-250 USD
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Αναρτήθηκε περίπου 7 χρόνια πριν
$30-250 USD
Πληρωμή κατά την παράδοση
I need some engineer to work on one of these topics (free to choose):
Notice : pay attention to all of the details and also the [*] and [**] at the end of the description.
1. An AXI Floating Point Unit : take the FPU of OpenCores and implement it on PL logic of the ZYNQ Z-7020, arm it with an AXI interface + [*] + [**]
2. Implement some type of Cryptography engines with AXI interfaces in the PL logic of ZYNQ Z-7020. (e.g. elliptic curve cryptography or AES) + [*] + [**]
3. Implement A CPU core with Morphing capability on PL logic of ZYNQ Z-7020. By morphing we mean the CPU core is capable of changing its architecture according to the type of work-load that it is executing. (to get more idea look at this paper: [login to view URL]) + [*] + [**]
4. Updating the UltraSparc T1 to talk AXI and implement it on PL logic of ZYNQ Z-7020. In this project, take the Simply RISC core and make it enable of talking AXI directly + [*]
5. Implement The 32 Bits AXI PicoBlaze on the PL logic of the ZYNQ Z-7020 ! The idea here is to have the stable and versatile PicoBlaze CPU core, then to increase its data-bus width to 32 Bits and then to add AXI plugs to its ports + [*] + [**]
6. Implement The AXI OpenRISC on the PL logic of the ZYNQ Z-7020. The basic idea is to have the OpenRISC core (either 1K or 1.2K or 2K) talking directly AXI. The OpenRISC core must have the data and instruction caches + [*] + [**]
[*] All of the listed projects should Import data from PC connected to the ZYNQ based board (using usb or ethernet) by using ARM processor and DMA of PS logic and transfer it to the implemented chosen logic of this list (in PL). After completion of data processing in the implemented chosen logic of this list (in PL), export data to PC by using ARM processor on the ZYNQ Z-7020 and DMA. Hence, a testbench should also be provided to test the whole implementation.
[**] All of the listed projects should model the chosen implementation with TLM and using SystemC language.
Hey!
I am professional FPGA developer and recently finished project of developing machine learning algorithms on Zynq ZedBoard.
I can help you with projects 1 and 5 .
[*] I developed such PL and PS connection on embedded linux and also on baremetal, but PC connection requirement, realistically needs more time to develop and also needs a complete development board to help u effectively and i can manage that being here in Germany and availability on tools and boards
[**] Xilinx provide HLS tools for high level synthesis which I used in my recent project. Modeling can also be done with SystemC with Xilinx tools. I think HLS will be much quicker, if you are constrained with time.
Please get in touch to know about my credentials and I can share my projects with you too as they are not on freelance platform but from my freelance employment in Germany.
Hi,
Can we discuss the project further?
I have done similar project and understood the project outline. Please give me a chance. A trial will convince you. Looking forward to work with you.