A synthesizable implementation of Search engines
(Search engines [input is pattern, data in memory, output is match address])
The implementation may be a mixed HW-SW approach.
May include multiple implementations, codes or algorithms.
Use data in block sizes of 512B, 1K, 2K, 4K
Memory input/output in 8, 16, 32 or 64 bits. Engine input/output left up to implementer
Clock of at least 50MHz (if using 90nm library)
The implementation may be a mixed HW-SW approach.
More information will be provided to bidders.