Altera connect I2S to Avalon and read write via linux/bare metal

It's mostly easy as it is beginner project, but I am new and so struggle a little myself.

Need:

I2S interface (for audio)

For lower bids will provide ip that needs to be hooked up

Using Verilog

Using Altera (Cyclone V SoC)

Interface with Avalon Bus (maybe master)

Write to DDR3

Simple C/C++ code to access the data from linux or like Bare metal code. something to do with DDR3 storage from avalon Bus

Requirements:

BCLK runs 16MHz1

left and right channel is 16 bits sample each side

I have Started the Verilog code, or will provide you with opensource i2s ip. Please do provide me with information how to load on QSYS how to run the testbench to test it's working. This will be my guide to learn how to use Altera and learn FPGA.

I'm using a cyclone V SOC (Altera dev kit soc), but any you can implement in other if needed, i can reassign pins later.

Resources I have used to help with the idea of I2S.

Specs: [url removed, login to view]

Tutorial:

[url removed, login to view]

Προγραμματισμός C++ FPGA Verilog / VHDL

Ταυτότητα Εργασίας: #14514910

Σχετικά με την εργασία